1. Field of the Invention
The present invention relates to a multi-gate field effect transistor and a method for manufacturing the multi-gate field effect transistor.
2. Related Art
Highly-integrated LSIs with high performances have been achieved by reducing the sizes of field effect transistors (FETs) as the fundamental elements of LSIs and improving the performances of those field effect transistors. The performance of each FET is determined by how high the driving current is during an ON operation and how low the leakage current from the channel is in an OFF state. According to the International Semiconductor Roadmap, novel techniques for realizing higher driving current and lower leakage current are necessary after the 45-nm generation.
To reduce the leakage current, fully-depleted (FD) devices each having its channel region fully depleted are expected as the next-generation fundamental devices, as the FD devices have high resistance to short channel effects. Particularly, attention is drawn to multi-gate field effect transistors among those devices. For example, a multi-gate field effect transistor has such a structure that a very small channel region is surrounded by gate electrodes, which is different from a single-gate field effect transistor that controls the potential in the channel from one direction only by a gate electrode formed on the surface of the channel as disclosed in JP-A 2005-86024 (KOKAI). The advantages of this structure are that the potential controllability in the channel region is made higher, a reduction of the potential barrier due to the shorter channel of each device is prevented, and the leakage current caused in an OFF state is lowered.
Here, controlling the threshold value of each device is essential. A FD device characteristically has inversion charges generated at a lower voltage than in a case of a bulk-type device. Therefore, if a conventional gate electrode material is used in a FD device, the leakage current in an OFF state (at 0 volt) becomes too high, and a new gate electrode material is required. At present, such gate electrodes include a type that uses a metal as a gate electrode (a metal gate), and a type that uses a compound of a metal and a semiconductor. The former is referred to a metal gate, the latter is referred to a silicide gate when the semiconductor is silicon and the compound is a silicide.
In a case where a metal gate and a silicide gate are used in a three-dimensional multi-gate field effect transistor, problems are caused in the manufacturing process. Particularly, metal contamination is always the biggest problem. To achieve a very small gate length, a flat surface is necessary when lithographic patterning is performed before the gate electrode is processed. However, the metal used in the metal gate or the silicide gate might enter the base semiconductor (such as silicon) or the gate insulating film, and the metal might become the center of carrier recoupling, charge traps, or a leakage current path. As a result, the device performance is greatly degraded. Therefore, flattening cannot be performed directly on the metal gate electrode or the silicide electrode by CMP (Chemical Mechanical Polishing). Also, the existence of a natural oxide film becomes a problem when a gate electrode is silicided. However, by any conventional manufacturing method, the natural oxide film cannot be removed.